1. Field of the Invention
The present invention relates to a Digital to Analogue converter provided with a capacitor array and an Analogue to Digital using the above-mentioned D/A converter.
2. Description of the Related Art
In general, the principle of electric charges distribution in an capacitor array is utilized in an A/D converter and D/A converter of the CMOS IC. For example, there is disclosed in JP2001-53610A a three step cyclic A/D converter employing a multiplying D/A converter. Further, there is disclosed a two step cyclic A/D converter employing a multiplying D/A converter in IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1996 December, Vol. 31, No. 12, p.2030-2035, xe2x80x9cA 12-b, 10 MHz, 250 mW CMOS A/D converterxe2x80x9d, G. C. Ahn et al.
FIG. 17 is a circuit diagram of a conventional two step cyclic A/D converter (ADC) with multiplying D/A converter (MDAC) similar to that as disclosed in the above-mentioned TEEE article. The ADC 1 comprises: a 5-bit ADC 2; a capacitor array 3 comprising capacitors C0, C1, . . . , C31 and CF; switches SW0, SW1, . . . , S31 and SF connected with each electrode of C0, C1, . . . , C31 and CF, respectively; a switch S32; and an adder 5.
Capacitance values of C0, C1, . . . and C31 are xe2x80x9cCxe2x80x9d, while a capacitance value of CF is xe2x80x9c2Cxe2x80x9d. On an actual semiconductor chip, CF is a parallel connection of CF0 and CF1 of which capacitance values are xe2x80x9cCxe2x80x9d. ADC 2 executes a 5-bit A/D conversion twice and the adder 5 adds a conversion code xe2x80x9cn1xe2x80x9d of the first A/D conversion and conversion code xe2x80x9cn2xe2x80x9d of the second A/D conversion, thereby obtaining a 9-bit A/D conversion.
FIG. 18 shows an exemplary arrangement of the capacitor array, wherein a common line connected with common electrodes of C0, C1, . . . , C31, CF0 and CF1 is easily disposed without adjoining or crossing other lines, thereby reducing a parasitic capacitance between the common line 6 and other lines and reducing a degradation in a conversion accuracy.
Here, regarding a structure of the capacitors, it may be a SiO2 layer between poly-Si layers, or an inter-layer film between adjacent Al wiring layers among multi-layer wiring layers. The capacitance values of the capacitors are not made perfectly the same, because it is difficult to make a thickness of SiO2 or inter-layer film perfectly uniform over the entire semiconductor chip.
Further, the linearly arranged capacitors as shown in FIG. 18 is affected by the film thickness distribution on the semiconductor chip, because the capacitor array becomes inevitably long. Thus, the non-linearity error and differential non-linearity error in the D/A or A/D conversion are increased.
An object of the present invention is to provide a D/A converter (DAC) and A/D converter (ADC) using the same wherein a high conversion accuracy is obtained, even when there exists a slope in an insulator film thickness distribution of capacitors for a capacitor array connected both with an A/D conversion circuit of an ADC and operational amplifier of a DAC.
The DAC of the present invention comprises: a capacitor array for storing electric charges in accordance with a digital voltage signal; and an operational amplifier of which input terminal is connected with the capacitor array and amplifies a voltage which corresponds to the electric charges.
Here, the capacitor array comprises a plurality of unit capacitors which comprises 2n divisional capacitors which are of the same shape and are connected in parallel, where xe2x80x9cnxe2x80x9d is a prescribed natural number.
Concretely, the DAC of the present invention includes fundamental seven Features as stated below.
Feature 1 resides in that the divisional capacitors are linearly disposed in mirror symmetry about a center line perpendicular to a longitudinal direction of the linear disposition of the capacitors; and one half of the divisional capacitors every the unit capacitor is disposed at one side of the center line and another half of the divisional capacitors is disposed at the another side of the center line.
According to Feature 1, when there exists a slope in the insulator film thickness distribution of the capacitors, the capacitance values of the divisional capacitors disposed at both sides of the center line are shifted by an equal quantity and moreover in the opposite direction with each other about the center line. Therefore, this is equivalent to such an arrangement that all the unit capacitors are formed on the center line. Accordingly, even when the insulator film thickness of the capacitance changes in a constant rate along the capacitor arrangement direction, the electric charge re-distribution error which causes the D/A conversion error can be made zero, theoretically. Even if the slope of the film thickness distribution function is not constant, the electric charge re-distribution error can be reduced as far as a linear approximation of the film thickness distribution function is employed.
Feature 2 resides in that the divisional capacitors are arranged in a plurality of rows and in center symmetry about a center point of the capacitor array.
According to Feature 2, similarly to Feature 1, the capacitance values of the divisional capacitors disposed at both sides of the center point are shifted by an equal quantity and moreover in the opposite direction with each other about the center point. Therefore, this is equivalent to such an arrangement that all the unit capacitors are formed at the center point. Accordingly, if the film thickness of the capacitor changes in a constant rate along the capacitor arrangement direction, the electric charge re-distribution error which causes the D/A conversion error can be made theoretically zero.
Feature 3 resides in that one of electrodes of each of the divisional capacitors is connected with a common line; and one half of the divisional capacitors every the unit capacitor is disposed at one side of the common line and another half of the divisional capacitors is disposed at the another side of the common line.
According to Feature 3, the arrangement length as a whole is shortened half, because the divisional capacitors are disposed at both sides of the common line. Accordingly, the capacitance deviation due to, e.g., a non-uniformity of etching and so on is reduced. Further, an increase in a capacitance due to a wiring between the divisional capacitors and common line is suppressed as small as possible.
Feature 4 resides in that dummy capacitors are disposed at edges or sides of the capacitor array.
According to Feature 4, the electrical conditions of the divisional capacitors are made uniform inside and outside the capacitor array, thereby reducing capacitance deviations of the divisional capacitors disposed at the edges or periphery of the capacitor array.
Feature 5 resides in that: (1) one of electrodes of each of the divisional capacitors for the electric charge re-distribution is connected with a common line; another electrode of each of the divisional capacitors is selectively connected with a prescribed reference voltage terminal or ground voltage terminal, in accordance with the digital voltage; and (2) another set of unit capacitors connected with an input terminal of the operational amplifier are provided for determining an D/A conversion gain.
According to Feature 5, a multiplying DAC is constructed.
Feature 6 resides in that the divisional capacitors for the electric charge redistribution are classified into xe2x80x9ckxe2x80x9d capacitors of which capacitance values are C, C, 2C, . . . , 2(kxe2x88x921)C, where xe2x80x9cCxe2x80x9d is a prescribed capacitance and xe2x80x9ckxe2x80x9d is a bit number of the digital voltage signal.
According to Feature 6, a number of switches for the electric charge re-distribution is reduced.
Feature 7 resides in that ADC is provided by using the above-mentioned DAC.
The ADC comprises: an A/D conversion circuit for converting an input voltage into a digital voltage; a capacitor array for storing electric charges in accordance with the input voltage; and an operational amplifier for converting a voltage corresponding to the electric charges into an analogue voltage. Here, one-side electrodes of the unit capacitors are selectively connected with a prescribed reference voltage terminal or ground voltage terminal in accordance with the digital voltage, while the other-side electrodes of the unit capacitors are connected with an inverting terminal of the operational amplifier. The A/D conversion circuit converts the input voltage into the digital voltage on the basis of the prescribed reference voltage.
According to Feature 7, a high accuracy ADC is obtained.
Furthermore, another Feature resides in that the above-mentioned divisional capacitor may comprises a plurality of sub-divisional capacitors which are of another same shape and connected in series.
In general, it is advantageous for the high speed conversion to reduce the capacitance. However, if a capacitor area is made smaller in order to reduce its capacitance, the accuracy of the capacitance values are apt to be lowered due to random fluctuations in the capacitance values caused by accuracy in manufacturing processes.
The above-mentioned series connection of the sub-divisional capacitors has an advantage that the capacitance of the divisional capacitor is reduced without wotiout employing a small area capacitor.
According to the above-mentioned another Feature, the DAC or ADC becomes of high speed, without sacrificing the accuracy of each divisional capacitor.
Still another Feature resides in that the capacitor array may be a parallel connection of the divisional capacitors each of which comprises above-mentioned sub-divisional capacitors.
According to the above-mentioned still another Feature, the DAC or ADC does not only become of high speed, but also the conversion error is reduced by employing the mirror symmetry arrangement or common centroid arrangement, as already explained.